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Philips Semiconductors RF Communications Products
Product specification
Divide by: 128/129-64/65 dual modulus low power ECL prescaler
SA701
DESCRIPTION
The SA701 is an advanced dual modulus (Divide By 128/129 or 64/65) low power ECL prescaler. The minimum supply voltage is 2.7V and is compatible with the CMOS UMA1005 synthesizer from Philips and other logic circuits. The low supply current allows application in battery operated low-power equipment. Maximum input signal frequency is 1.1GHz for cellular and other land mobile applications. There is no lower frequency limit due to a fully static design. The circuit is implemented in ECL technology on the QUBiC process. The circuit will be available in an 8-pin SO package with 150 mil package width and in 8-pin dual in-line plastic package, and is pin compatible with Fujitsu MB501, Plessey SP8704 and Motorola MC12022.
FEATURES
* Low voltage operation * Low current consumption * Operation up to 1.1GHz * ESD hardened
APPLICATIONS
PIN CONFIGURATION
N, D Package
1 2 3 4 8 7 6 5 IN nc MC GND
IN VC
C SW
OUT
* Cellular phones * Cordless phones * RF LANs * Test and measurement * Military radio * VHF/UHF mobile radio * VHF/UHF hand-held radio
ORDERING INFORMATION
DESCRIPTION 8-Pin Plastic Dual In-Line Package (DIP) 8-Pin Plastic Small Outline (SO) package (Surface-mount) TEMPERATURE RANGE -40 to +85C -40 to +85C ORDER CODE SA701N SA701D DWG # 0404B 0174C
ABSOLUTE MAXIMUM RATINGS
SYMBOL VCC VIN IO TSTG TA JA Supply voltage Voltage applied to any other pin Output current Storage temperature range Operating ambient temperature range Thermal impedance D package N package PARAMETER RATING -0.3 to +7.0 -0.3 to (VCC + 0.3) 10 -65 to +125 -55 to +125 158 108 UNITS V V mA C C C/W
June 17, 1993
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853-1708 10044
Philips Semiconductors RF Communications Products
Product specification
Divide by: 128/129-64/65 dual modulus low power ECL prescaler
SA701
BLOCK DIAGRAM
OUT Q D Q D Q D Q Q D Q D Q Q D Q D Q D Q MC IN IN
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SW
Philips Semiconductors RF Communications Products
Product specification
Divide by: 128/129-64/65 dual modulus low power ECL prescaler
SA701
DC ELECTRICAL CHARACTERISTICS
The following DC specifications are valid for TA = 25C and VCC = 3.0V; unless otherwise stated. Test circuit Figure 1. SYMBOL VCC ICC VOH VOL VIH VIL VIH VIL IIH IIL IIH IIL PARAMETER Power supply voltage range Supply current Output high level Output low level MC input high threshold MC input low threshold SW input high threshold SW input low threshold MC input high current MC input low current SW input high current SW input low current VMC = VCC = 6V VMC = 0V, VCC = 6V VSW = VCC = 6V VSW = 0V, VCC = 6V -50 -100 2.0 -0.3 2.0 -0.3 0.1 -30 35 -0.1 100 TEST CONDITIONS MIN fIN = 1GHz, input level = 0dBm No load IOUT = 1.2mA VCC-1.4 VCC-2.6 VCC 0.8 VCC 0.8 50 2.7 4.5 LIMITS TYP MAX 6.0 V mA V V V V V V A A A A UNITS
AC ELECTRICAL CHARACTERISTICS
The following AC specifications are valid for VCC = 3.0V, fIN = 1GHz, input level = 0dBm, TA = 25C; unless otherwise stated. Test circuit Fig. 1. SYMBOL VIN fIN RID VO tS tH tPD PARAMETER Input signal amplitude1 Input signal frequency Differential input resistance Output voltage Modulus set-up time1 Modulus hold time1 Propagation time 10 TEST CONDITIONS MIN 1000pF input coupling Direct coupled input2 1000pF input coupling DC measurement VCC = 5.0V VCC = 3.0V 5 1.6 1.2 5 0 0.05 0 LIMITS TYP MAX 2.0 1.1 1.1 VP-P GHz GHz k VP-P VP-P ns ns ns UNITS
NOTES: 1. Maximum limit is not tested, however, it is guaranteed by design and characterization. 2. For fIN < 50MHz, minimum input slew rate of 32V/s is required.
DESCRIPTION OF OPERATION
The SA701 comprises a frequency divider circuit implemented using a divide by 4 or 5 synchronous prescaler followed by a 5 stage synchronous counter, see BLOCK DIAGRAM. The normal operating mode is for SW (Modulus Set Switch) input to be set low and MC (Modulus Control) input to be set high in which case the circuit comprises a divide by 128. For divide by 129 the MC signal is forced low, causing the prescaler circuit to switch into divide by 5 operation for the last cycle of the synchronous counter. Similarly, for divide by 64 and 65 the SA701 will generate those respective moduli with the SW signal forced high, in which the fourth stage of the synchronous divider is
bypassed. A truth table for the modulus values is given below:
Table 1.
Modulus 128 129 64 65 MC 1 0 1 0 SW 0 0 1 1
the input. The rising edge of the output occurs at the count 64 for modulus 128/129 or count 32 for modulus 64/65 with delay tPD. The SW input is not designed for synchronous switching. The MC and SW inputs are TTL compatible threshold inputs operating at a reduced input current. CMOS and low voltage interface capability are allowed. The SW input has an internal pull-down simplifying modulus group selection. With SW open the divide by 128/129 mode is selected and with SW connected to VCC divide by 64/65 is selected. The prescaler input is differential and ECL compatible. The output is single-ended ECL compatible.
For minimization of propagation delay effects, the second divider circuit is synchronous to the divide by 4/5 stage output. The prescaler input is positive edge sensitive, and the output at the final count is a falling edge with propagation delay tPD relative to
June 17, 1993
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Philips Semiconductors RF Communications Products
Product specification
Divide by: 128/129-64/65 dual modulus low power ECL prescaler
SA701
AC TIMING CHARACTERISTICS
COUNT IN
128
129
1
64
127
128
1
MC
OUT
tP
tS SW = 0. DIVIDE BY 128/129 OPERATION.
tH
D
COUNT IN 127 128 1 64 127 128 129 1
MC
OUT
tP
tS SW = 0. DIVIDE BY 128/129 OPERATION.
tH
D
COUNT IN
64
65
1
32
63
64
1
MC
OUT
tP
tS SW = 1. DIVIDE BY 64/65 OPERATION.
tH
D
COUNT IN 63 64 1 32 63 64 65 1
MC
OUT
tP
tS SW = 1. DIVIDE BY 64/65 OPERATION.
tH
D
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Philips Semiconductors RF Communications Products
Product specification
Divide by: 128/129-64/65 dual modulus low power ECL prescaler
SA701
IN
IN
50
50
R1 50
C1 1000pF
C2 1000pF
R2 50
IN
IN
VCC
VCC
NC
SW C3 0.1F
SW
MC
MC
OUT
GND
OUT
R3 2.2k
C4 5pF
Figure 1. SA701 Test Circuit
FREQUENCY (MHz) 0 200 -5 MINIMUM INPUT POWER (dBm) 400 600 800 1000 1200
-10 -40C VCC = 3.0V -20 25C 85C
-15
-25
-30
-35
-40
Figure 2. Minimum Input Power vs Frequency and Temperature
June 17, 1993
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Philips Semiconductors RF Communications Products
Product specification
Divide by: 128/129-64/65 dual modulus low power ECL prescaler
SA701
FREQUENCY (MHz) 0 200 -5 MINIMUM INPUT POWER (dBm) -10 -15 TA = 25C -20 -25 -30 -35 -40 2.7V 3.0V 6.0V 400 600 800 1000 1200
Figure 3. Minimum Input Power vs Frequency and VCC
6 85C 5.5
25C 5 ICC (mA)
4.5 -40C 4
3.5
3 2.7 3 VCC (V) 6 7
Figure 4. Supply Current vs Supply Voltage and Temperature With No Load
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Philips Semiconductors RF Communications Products
Product specification
Divide by: 128/129-64/65 dual modulus low power ECL prescaler
SA701
j1
j0.5
j2
VCC = 3V j0.2 j5 TA = 25C
0
0.2
0.5
1
2
5 50
INPUT
R3 4
L4 6nH
300 -j0.2 600 -j5
C2 0.4pF
R1 3000
C1 0.9pF
EQUIVALENT INPUT IMPEDANCE 900
-j0.5
1200
-j2
-j1
Figure 5. Typical N Package Input Impedance
j1
j0.5
j2
j0.2
j5
VCC = 3V TA = 25C L4 3nH
0
0.2
0.5
1
2
5 50
INPUT
R3 2
C2 0.2pF 300 -j0.2 600 -j5
R1 3000
C1 0.9pF
EQUIVALENT INPUT IMPEDANCE 900 -j2
-j0.5
1200
-j1
Figure 6. Typical D Package Input Impedance
June 17, 1993
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